1. Field of the Invention
The present invention relates to a fabrication method of a field-effect transistor (FET) and more particularly, to a fabrication method of a compound semiconductor FET having an offset-gate electrode in a recess of a semiconductor layer, which enables to control separately a length between one edge of the recess and an opposed end of the gate electrode and a length between the other edge of the recess and the other opposed end of the gate electrode.
2. Description of the Prior Art
It has been known that a compound semiconductor heterojunction FET is superior in gain and noise to a silicon FET, that is, the former is higher in gain and lower in noise than the latter. Such the compound semiconductor FET contains a heterojunction of a first compound semiconductor (for example, AlGaAs) layer with a relatively lower electron affinity and a second compound semiconductor (for example, GaAs) layer with a relatively higher electron affinity.
With the first and second semiconductor layers of this FET, electrons as carriers within the first semiconductor layer tend to move into the second semiconductor layer to form an electron accumulation layer in the vicinity of the heterojunction inside the second semiconductor layer, resulting in a 2-dimension electron gas in the electron accumulation layer. A bias voltage applied to a gate electrode changes the electron density of the electron gas and as a result, the bias voltage can control a current flowing between a source electrode and a drain electrode disposed at each side of the gate electrode. The gate electrode is placed on the bottom of a recess formed between the source and drain electrodes.
The heterojunction FET of this type has already been put to practical use as a low noise device for the ultra-high frequency (UHF) band, which is especially proper for the 4 GHz band or higher.
With the heterojunction FET of this type, the series resistance R.sub.S between the source and drain electrodes is strongly dependent on the bottom length of the recess at the source side. Especially, in small current applications requiring sufficiently low noise characteristics, the electron density of the 2-dimension electron gas is limited to a low value at a position right below the gate electrode, and therefore, the series resistance R.sub.S increases. The resistance R.sub.S thus increased seriously affects the noise characteristic of this heterojunction FET.
Accordingly, the bottom length of the recess at the source side should be designed to be possibly short in view of the FET performance.
On the other hand, the gate-drain capacitance C.sub.gd between the gate electrode and the drain electrode is dependent on the bottom length of the recess at the drain side. The capacitance C.sub.gd increases as the length decreases, and the capacitance thus increased causes deterioration of the FET performance such as a power gain in high-frequency applications.
Also, in high-output applications where both backward breakdown voltages of the gate electrodes and source-drain withstand voltages between the source and drain electrodes are high, the bottom length of the recess at the drain side should be typically longer than the bottom length of the recess at the source side in view of the FET performance.
Thus, more recently, the bottom length of the recess at the drain side has been designed to be longer than that at the source side, which is termed the "offset-gate structure" because the gate electrode is out of the longitudinal center of the recess.
Examples of conventional compound semiconductor FETs of this type having the offset-gate structure have been disclosed in the Japanese Non-Examined Patent Publication Nos. 3-145140 (published in June, 1991) and 61-154177 (published in July, 1986).
FIGS. 1A and 1B show the conventional FET disclosed in the Publication No. 3-145140, which is fabricated by the following process sequence:
First, as shown in FIG. 1A, a semiconductor substructure 41 is prepared, which is made of a semi-insulating GaAs substrate and some compound semiconductor layers such as a channel layer and a carrier-supply layer stacked on the substrate. The substructure 41 has source and drain electrodes (not shown) on its top surface.
Next, a silicon dioxide (SiO.sub.2) film 42 is formed on the top surface of the substructure 41 to cover the source and drain electrodes by a chemical vapor deposition (CVD) process.
A first photoresist film 43 is then formed on the SiO.sub.2 film 42 to be patterned, producing three windows 45-1, 45-2 and 45-3 that penetrate the film 43 between the source and drain electrodes. Using the photoresist film 43 thus patterned as a mask, the SiO.sub.2 film 42 is selectively etched so that the film 42 has three penetrating holes placed at the corresponding positions to the windows 45-1, 45-2 and 45-3, respectively. Thus, the top surface of the substructure 41 is exposed from the first photoresist film 43 and the SiO.sub.2 film 42 through the windows 45-1, 45-2 and 45-3 and the corresponding holes of the film 42.
A second photoresist film 44 is formed on the first photoresist film 43 to be patterned, producing a window 46 that penetrates the film 44 at a corresponding position to the central window 45-2 of the first photoresist film. Thus, the top surface of the substructure 41 is exposed from the first and second photoresist films 43 and 44 through the windows 45-2 and 46. The windows 45-1 and 45-2 of the first photoresist film 43 and the corresponding penetrating holes of the SiO.sub.2 film 42 are filled with the material of the second photoresist film 44.
Subsequently, the SiO.sub.2 film 42 is partially etched between the windows 45-1 and 45-3 through the window 46. Then, using the first and second photoresist films 43 and 44 thus patterned as a mask, the top surface of the substructure 41 is selectively etched through the windows 45-2 and 46 and the corresponding penetrating hole, producing a recess 47, as shown in FIG. 1B. The width of the recess 47 is defined by the windows 45-1 and 45-3.
Finally, a titanium-aluminum (Ti--Al) alloy film 48 is formed on the second photoresist film 44 to cover the window 46, and it is then removed with the first and second photoresist films 43 and 44 by a lift-off method. Through this process, only the part 48g of the Ti--Al film 48 is left in the recess 47, as shown in FIG. 1B, which acts as a gate electrode of this FET. The gate electrode 48g has a width L.sub.g at its bottom.
The bottom length L.sub.41 of the recess between the sourceside bottom edge of the recess 47 and the opposite bottom edge of the gate electrode 48g is substantially equal to the length between the source-side edge of the central window 45-2 and the opposite edge of the source-side window 45-1 of the first photoresist film 43.
Similarly, the bottom length L.sub.42 of the recess between the drain-side bottom edge of the recess 47 and the opposite bottom edge of the gate electrode 48g is substantially equal to the length between the drain-side edge of the central window 45-2 and the opposite edge of the drain-side window 45-3 of the first photoresist film 43.
Since the length L.sub.42 is longer than the length L.sub.41, the gate electrode 48g is out of the longitudinal center of the recess 47, which means that the conventional compound semiconductor FET of FIGS. 1A and 1B has the offset-gate structure described previously.
FIGS. 2A and 2B show the conventional FET disclosed in the Publication No. 61-154177, which is fabricated by the following process sequence:
First, as shown in FIG. 2A, a semiconductor substructure 51 is prepared, which is made of a semi-insulating GaAs substrate and some compound semiconductor layers such as a channel layer and a carrier-supply layer stacked on the substrate. The substructure 51 has source and drain electrodes (not shown) on its top surface.
Next, a silicon nitride (Si.sub.3 N.sub.4) film 52 is grown at a low temperature on the top surface of the substructure 51 to cover the source and drain electrodes by a plasma-enhanced CVD process. The film 52 is patterned to be left only at a corresponding area to a recess, as shown in FIG. 2A.
Then, a SiO.sub.2 film 53 is grown on the top surface of the substructure 51 to cover the patterned Si.sub.3 N.sub.4 film 52 by a CVD process 52, and a Si.sub.3 N.sub.4 film 54 is grown on the SiO.sub.2 film 53 thus grown through a plasma-enhanced CVD process.
A photoresist film 55 is formed on the Si.sub.3 N.sub.4 film 54 to be patterned, producing a window 56 that penetrates the film 55 between the source and drain electrodes. Using the photoresist film 55 thus patterned as a mask, the underlying Si.sub.3 N.sub.4 film 54 and the SiO.sub.2 film 53 are selectively removed by a dry etching process, producing a hole that penetrates the films 54 and 53 at a corresponding position to the window 56. The patterned Si.sub.3 N.sub.4 film 52 is exposed from the films 55, 54 and 53 at this stage.
Subsequently, the patterned Si.sub.3 N.sub.4 film 52 is entirely removed by a wet etching process and the photoresist film 55 is removed. Then, the top surface of the substructure 51 thus exposed is selectively removed through the penetrating hole of the Si.sub.3 N.sub.4 film 54 and the SiO.sub.2 film 53, producing a recess 57 as shown in FIG. 2B. The shape of the recess 57 is defined by the patterned Si.sub.3 N.sub.4 film 52.
Finally, a Ti--Al alloy film 58 is formed on the Si.sub.3 N.sub.4 film 54 to cover the hole penetrating the films 54 and 53, and is then removed with the films 53 and 54 by a lift-off method. Thus, only the part 58g of the Ti--Al film 58 is left in the recess 57, as shown in FIG. 2B, which acts as a gate electrode of this FET. The gate electrode 58g has a width L.sub.g at its bottom, which is defined by the width of the hole penetrating the films 53 and 54.
The bottom length of the recess between the source-side bottom edge of the recess 57 and the opposite bottom edge of the gate electrode 58g is L.sub.51. The bottom length of the recess between the drain-side bottom edge of the recess 57 and the opposite bottom edge of the gate electrode 48g is L.sub.52.
With the fabrication method of the conventional FET shown in FIGS. 1A and 1B, the window 46 of the second photoresist film 44 is required to be aligned with the central window 45-2 of the first photoresist film 43 through visual adjustment during the exposure process of the second photoresist film 44. Thus, practically, in consideration of the accuracy limits of the present photolithography and etching techniques, the bottom length L.sub.41 between the source-side bottom edge of the recess 47 and the opposite bottom edge of the gate electrode 48g is very difficult to be about 0.2 .mu.m or less.
Therefore, a problem that the series resistance R.sub.S between the source and gate electrodes cannot be satisfactorily reduced occurs.
with the fabrication method of the conventional FET shown in FIGS. 2A and 2B, the window 56 of the photoresist film 55 is required to be aligned with the patterned Si.sub.3 O.sub.4 film 52 at a possibly high accuracy through visual adjustment during the exposure process of the photoresist film 55.
The alignment accuracy of the present lithography technique has, however, a minimum limit of about .+-.0.1 .mu.m. Therefore, the high-frequency performance or characteristic of the FET varies within a considerably wide extent because of the fluctuations in the series resistance R.sub.S and the gate-drain capacitance C.sub.gd that is due to the positional fluctuations between the recess 57 and the gate electrode 58g.
As a result, another problem that the bottom length L.sub.51 of the recess between the source-side bottom edge of the recess 57 and the opposite bottom edge of the gate electrode 58g is very difficult to be designed about 0.2 .mu.m or less occurs.
Additionally, there is also the same problem as the conventional FET of FIGS. 1A and 1B relating to the series resistance R.sub.S.